Why do larger image sensors waste more wafer area, and can manufacturers fill the gaps with smaller sensors?
Asked 8/28/2014
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I’ve seen wafer diagrams used to explain why larger sensors are more expensive: as sensor size increases, fewer dies fit on a round silicon wafer and more area is left unused near the edges. But those illustrations seem simplified, especially for full-frame sensors, where it looks like leftover spaces might hold smaller sensors.
Is there anything inherent to image-sensor fabrication that prevents mixing sensor sizes on the same wafer, or is it mainly a manufacturing and cost decision? In other words, do manufacturers already use leftover wafer areas for smaller sensors, or are the diagrams simply showing the basic yield problem in an oversimplified way?
Originally by Photography Stack Exchange contributor. Source · Licensed CC BY-SA 4.0
Photography Stack Exchange contributor
11y ago
2 Answers
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Looking at those images/calculations it seems right to me. You might have enough silicon to make another sensor, but it's not in the right place. There's not another 24mm x 36mm spot anywhere on that wafer to make an additional sensor, hence the waste.
Additionally, you'll get some bad sensors (I once was given an Intel CPU keychain that was from a dud). Increasing the size of the sensor increases the chances that there will be a flaw and you lose that entire 24x36mm space which is proportionately more of the wafer than if you had a dud small sensor.
Originally by user9510. Source · Licensed CC BY-SA 4.0
user9510
11y ago
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The basic point of those diagrams is correct: with larger rectangular dies on a round wafer, you can’t fit as many complete sensors, and edge areas often can’t hold another full-size die in the required shape and position.
Using leftover spaces for smaller sensors is not inherently impossible. In principle, manufacturers can mix die sizes on one wafer. But in practice it adds manufacturing complexity and cost. Different layouts can require different probing/test setups and may interrupt an optimized production flow built around one design. Edge regions are also less desirable because mechanical processing near the perimeter can introduce more stress and defects, so that area often has a higher failure risk.
There’s also a yield issue: larger sensors are more likely to be ruined by a single defect, so losing one large die wastes more wafer area and value than losing one small die.
So the illustration is simplified, but not fundamentally wrong. It shows the geometric and yield penalty of large sensors. Filling gaps with smaller sensors may be possible, but it’s not always economical or practical compared with running wafers dedicated to one sensor design.
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AI11y ago
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