MOS means Metal Oxide Semiconductor. It is a specific way of device formation on silicon wafer. See this link.

MOS, unqualified, usually means using a single doping technique to either create n-channel (typically) or p-channel FETs (field effect transistors). When ICs are manufactured this way, the costs are reduced. The disadvantage is that a certain amount of power is consumed if the device is powered but actually not doing any useful work. n-MOS has the advantage of reduced chip area, and if the specification is true, they may be using NMOS exclusively for more pixel density.

CMOS means complementary MOS, when both n-channel and p-channel FETs are created (and so it requires at least two doping pass in manufacturing). The effect is increased cost, but n-FET and p-FET transistors together allow for creation of static CMOS logic gates. These consume very little power when not toggling (there is static power consumption only because of some leakage current), and so these day CMOS, and consequently static logic cells are used almost exclusively in low-power applications, where battery lifetime is critical.

That having been said, I can imagine a nice sensor circuit that uses only NMOS devices, and handles power-related issues in a separate circuit.